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IC62LV51216L IC62LV51216LL
Document Title
512 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A 0B
History
Draft Date
Remark
Initial Draft January 3,2002 1. Add CE2 pin for 48 pin TF-BGA September 2,2002 2. Change for ICC: 35 mA to 30 mA for 55 ns Industrial product 30 mA to 25 mA for 70 ns Industrial product 25 mA to 20 mA for 100 ns Industrial product 30 mA to 25 mA for 55 ns Commerical product 25 mA to 20 mA for 70 ns Commerical product 20 mA to 15 mA for 100 ns Commerical product 3. Change for ISB2: 20 A to 15 A for Commerical product 4. Change for IDR: 15 A to 20 A for Commerical/L product 6 A to 13 A for Commerical/LL product 20 A to 30 A for Industrial/L product 9 A to 23 A for Industrial/LL product 1. Revise typo for pin assignment H1 from NC to A18 January 22,2003 2. Change Truth Table of LB/UB control,CE1 and CE2 to "Don't care" 3. Change DC parameters for TSOP-2 package as follows (1)VIH : 2.2V to 2.8V (2)ISB1 : 0.2mA to 0.7mA for commercial product 0.3mA to 0.8mA for Industrial product (3)ISB2 : 15A to 20A for commercial/LL product 25A to 30A for Industrial/LL product (4)ICC : 25mA to 30mA for commercial/LL product 30mA to 35mA for Industrial/LL product
0C
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR014-0C 1/22/2003
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IC62LV51216L IC62LV51216LL
512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
* High-speed access times: 55, 70, 100 ns * CMOS low power operation ICC=18mA (typical)* operating ISB2=3A (typical)* CMOS standby * TTL compatible interface levels * Single 2.7V-3.6V Vcc power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * Available in the know good die from 44-pin TSOP-2 and 48-pin 8x10mm TF-BGA * CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at VCC=3.0V, TA=25C
DESCRIPTION The ICSI IC62LV51216L and IC62LV51216LL are low-power,
8.388,608 bit static RAMs organized as 524,288 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE1 is HIGH or when CE2 is low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV51216L and IC62LV51216LL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE1/ CE2 OE WE UB LB CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
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IC62LV51216L IC62LV51216LL
PIN CONFIGURATIONS
44-Pin TSOP-2
A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13
48-Pin TF-BGA (TOP View)
1 A B C D E F G H
LB I/O8 I/O9 GND Vcc
2
OE UB I/O10 I/O11 I/O12
3
A0 A3 A5 A17 NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6
CE2 I/O0 I/O2 Vcc GND I/O6 I/O7 NC
I/O14 I/O13 I/O15 A18 NC A8
PIN DESCRIPTIONS
A0-A18 I/O0-I/O15 CE1 CE2 OE WE Address Inputs Data Input/Output Chip Enable1 Input Chip Enable2 Input, BGA only Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (l/O0-I/O7) Upper-byte Control (l/O8-I/O15) No Connection Power Ground
TRUTH TABLE
Mode Not Selected WE CE1 H X X L L L L L L L L CE2 2 X L X H H H H H H H H OE X X X H H L L L X X X LB X X H L X L H L L H L UB X X H X L H L L H L L I/O0/-I/O7 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O PIN I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current Standby Standby Standby Active Active Active Active Active Active Active Active
X X X Output Disabled H H Read H H H Write L L L
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IC62LV51216L IC62LV51216LL
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V- 3.6V 2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation Value -0.5 to Vcc + 0.5 -40 to +85 -0.3 to +4.0 -65 to +150 1.0 Unit V C V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH(1) VIL(2) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions IOH = -1 mA IOL = 2.1 mA Min. 2.0 -- 2.2 2.8* -0.2 -1 -1 Max. -- 0.4 VCC + 0.2 VCC + 0.2 0.4 1 1 Unit V V V V A A
GND VIN VCC GND VOUT VCC, OUTPUTS DISABLED
Notes: 1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns. 2. VIL(min.) = -2.0V for pulse width less than 10 ns. *. For TSOP-2
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters.
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AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V 1.5V See Figures 1 and 2
AC TEST LOADS
1 TTL OUTPUT 100 pF Including jig and scope OUTPUT 5 pF Including jig and scope 1 TTL
Figure 1
Figure 2
IC62LV51216L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = 3.0V., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, f = 0 CE1 = VIH, CE2 = VIL Com. Ind. Com. Ind. Com. Ind. -55 Min. Max. -- -- -- -- -- -- -- -- 30 35 0.2 0.3 0.7* 0.8* 35 50 -70 Min. Max. -- -- -- -- -- -- -- -- 25 30 0.2 0.3 0.7* 0.8* 35 50 -100 Min. Max. -- -- -- -- -- -- -- -- 20 25 0.2 0.3 0.7* 0.8* 35 50 Unit mA mA
ISB2
CMOS Standby Current (CMOS Inputs) OR ULB Control
VCC = Max., Com. CE1 VCC - 0.2V, Ind. or CE2 0.2V other input = 0-VCC, f = 0
A
VCC = Max., CE1 = VIL, CE2 = VIH VIN 0.2V, f = 0, UB / LB VCC - 0.2V
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. *.For TSOP-2
Integrated Circuit Solution Inc.
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IC62LV51216L IC62LV51216LL
IC62LV51216LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC Vcc Dynamic Operating Supply Current Test Conditions VCC = 3.0V IOUT = 0 mA, f = fMAX Com. Ind. Com. Ind. Com. Ind. Com. Ind. -55 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- 25 30 30* 35* 0.2 0.3 0.7* 0.8* 15 25 20* 30* -70 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- 20 25 25* 30* 0.2 0.3 0.7* 0.8* 15 25 20* 30* -100 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- 15 20 20* 25* 0.2 0.3 0.7* 0.8* 15 25 20* 30* Unit mA
ISB1
TTL Standby Current (TTL Inputs)
VCC = Max., VIN = VIH or VIL, CE1 = VIH, CE2 = VIL
mA
ISB2
CMOS Standby Current (CMOS Inputs)
VCC = Max., f = 0 Com. CE1 VCC - 0.2V, Ind. or CE2 0.2V Com. other input = 0-VCC, f = 0 Ind. OR
A
ULB Control
VCC = Max., CE1 = VIL, CE2 = VIH VIN 0.2V, f = 0, UB / LB VCC - 0.2V
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. *. For TSOP-2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time Min. 55 -- 10 -- -- -- 5 0 10 -- 0 0 Max. -- 55 -- 55 30 20 -- 20 -- 55 25 -- Min. 70 -- 10 -- -- -- 5 0 10 -- 0 0 -70 Max. -- 70 -- 70 38 25 -- 25 -- 70 25 -- -100 Min. Max. 100 -- 15 -- -- -- 5 0 10 -- 0 0 -- 100 -- 100 50 30 -- 30 -- 100 35 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE
tHZOE(2) OE to High-Z Output tLZOE(2) OE to Low-Z Output tHZCE tLZCE tBA tHZB tLZB
(2)
CE1 or CE2 to High-Z Output CE1 and CE2 to Low-Z Output LB, UB Access Time LB, UB o High-Z Output LB. UB to Low-Z Output
(2)
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
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AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled) (CE1 = OE = VIL, CE2 = VIH, UB or LB = VIL)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (OE, Controlled)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE1
tLZOE
CE2
tACE tLZCE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, UB, or LB = VIL, CE2 = VIH 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
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IC62LV51216L IC62LV51216LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55 Symbol Parameter Write Cycle Time CE1 Low and CE2 HIGH to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End
(3)
-70 Max. -- -- -- -- -- -- -- -- -- 30 -- Min. 70 65 65 0 0 60 55 30 0 -- 5 Max. -- -- -- -- -- -- -- -- -- 30 --
Min. 55 50 50 0 0 45 45 25 0 -- 5
-100 Min. Max 100 80 80 0 0 80 80 40 0 -- 5 -- -- -- -- -- -- -- -- -- 40 --
Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE
WE LOW to High-Z Output
tLZWE(3) WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE1 or CE2, Controlled, OE =
HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
t SA
CE1
t SCE
t HA
CE2
t AW t PWE
WE
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB and UB inputs being in the LOW state.
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IC62LV51216L IC62LV51216LL
WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
t SCE
CE1
CE2 WE
t AW t PWE t SA t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE CE1
LOW
t HA t SCE
CE2
t AW t PWE
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
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IC62LV51216L IC62LV51216LL
WRITE CYCLE NO. 4 (UB / LB Controlled)
t WC
ADDRESS
ADDRESS 1
t WC
ADDRESS 2
OE
t SA
CE1
CE2
WE
t HA t SA t PBW t PBW
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform VCC = 1.5V, CE1 VCC - 0.2V
(1)
Min. 1.5 Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) -- -- -- -- 0
Max. 3.6 20 13 30 23 -- --
Unit V A
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
ns ns
10
Notes: 1. 1) CE1 VCC -0.2V, CE2 VCC -0.2V, (CE1 controlled) or 2) 0V CE2 0.2V (CE2 controlled) or 3) LB = UB VCC -0.2V, CE2 VCC -0.2V (LB/UB controlled)
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IC62LV51216L IC62LV51216LL
DATA RETENTION WAVEFORM (CE1 Controlled)
tSDR VCC 1.65V Data Retention Mode tRDR
1.4V
VDR CE1 VCC - 0.2V
CE1 GND
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IC62LV51216L IC62LV51216LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 55 70 100 IC62LV51216L-55T IC62LV51216L-55B IC62LV51216L-70T IC62LV51216L-70B IC62LV51216L-100T IC62LV51216L-100B Package TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 55 70 100 IC62LV51216L-55TI IC62LV51216L-55BI IC62LV51216L-70TI IC62LV51216L-70BI IC62LV51216L-100TI IC62LV51216L-100BI Package TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 55 70 100 IC62LV51216LL-55T IC62LV51216LL-55B IC62LV51216LL-70T IC62LV51216LL-70B IC62LV51216LL-100T IC62LV51216LL-100B Package TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 55 70 100 IC62LV51216LL-55TI IC62LV51216LL-55BI IC62LV51216LL-70TI IC62LV51216LL-70BI IC62LV51216LL-100TI IC62LV51216LL-100BI Package TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA TSOP-2 8*10mm TF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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